Capstone Design Project A (Fall, 2019)
Capstone Design Project A&B (Graduation Project)
Prof. Hyunsu Kim
In this project, DRAM and nonvolatile next-generation memory (NVRAM, LPM) to reduce the power consumption of memory (hereinafter HM: Hybrid Memory) and processor
Dynamically adjust the voltage to lower the power consumption of the processor (hereinafter DVFS: Dynamic VoltageFrequency Scaling) to maximize the power saving effect of the system.
We improved the proposed method compared to the control group according to utilization in single-core and multi-core environments
Also, we compared and analyzed its performance. In addition, each suboptimal algorithm such as the genetic algorithm and low power technology is used to further reduce power consumption by pre-determining the frequency/voltage and memory of the processor to be allocated to the task.
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